It is well known that faster computer systems are generally more desirable than the slower computer systems because the faster computer systems can process more data and provide faster feedback to users. One approach in designing computer systems in order to increase the speed of the computer system is to provide a cache memory which, while expensive, is faster than conventional, cheaper memory. The cache memory is used to store more frequently accessed data and can operate at a higher frequency than the cheaper, slower conventional memory. An example of faster cache memory is conventional static random access memory (SRAM) which may operate with microprocessors having operating frequencies greater than 100 MHz. While it would be possible to implement all of the computer's system memory using fast SRAM, this is an expensive proposition. Implementing a portion of the memory used by the processor in cache which is made from SRAM provides a price/performance tradeoff--the slow DRAM memory may be large in order to store larger amounts of data and instructions while the SRAM may provide high speed performance for frequently accessed data and/or instructions.
FIG. 1a shows a typical implementation of a computer system in the prior art, which implementation includes a cache memory array, in the form of SRAM, along with slower dynamic random access memory (DRAM). A conventional microprocessor 10, such as a Pentium microprocessor is coupled to a processor bus 11 which includes data and address lines as well as control lines. The cache memory array 12, a system control and cache/DRAM control 15 and a data path logic unit 23 are also coupled to the processor bus 11. DRAM 25, typically comprising a plurality of DRAM integrated circuits (ICs), is coupled to the processor bus 11 through the data path logic 23 and typically receives address signals from the processor bus 11 through the interconnect bus 16 which is coupled to the system control and cache/DRAM control unit 15. The system control and cache/DRAM control unit 15 will be appreciated to be the conventional core logic chipsets which are provided by numerous vendors. These chipsets act as "glue" logic to coordinate the interaction of the components of the computer system, including the microprocessor and the processor bus as well as the cache and the DRAM memory and to also provide an interface to an expansion bus, such as a PCI bus. In FIG. 1a, the bus 19 may be a PCI bus and is coupled to the system control and cache/DRAM control unit 15. The system control and cache/DRAM control unit 15 is also coupled to a tag RAM 14 which is used to store a directory of entries in the cache RAM array. As is well known, the tag RAM stores addresses of system memory which have been cached into the cache memory; when the processor requests data by providing an address over the processor bus 11, the system control unit 15 reads that address and checks the tag RAM 14, which is normally implemented in fast SRAM 12 to determine whether the data requested by the processor is stored in the cache SRAM. If it is not, the system control and cache/DRAM control unit 15 then requests the data from the DRAM 25 utilizing the data path logic unit 23 and the interconnect bus 16 to retrieve the data from the DRAM 25 via the data path logic unit 23. At the same time, depending on the write policy implemented in the computer system relative to the cache array, the same data is provided to the cache to update the cache array 12. Since the use of cache in computer systems is well known, much of the details concerning cache operation will not be reiterated here.
The computer system shown in FIG. 1a, also typically includes a bus 19 which is coupled to a graphics controller 17 and to a peripheral controller 21. The graphics controller 17 typically includes a frame buffer which is used to drive a CRT 18 to provide an output to a user of the computer system. The peripheral controller 21 controls the operation including the input and output operation of a peripheral unit such as the peripheral device 20. It will be appreciated that the peripheral 20 may be a hard disk or a network controller. In one implementation, the bus 19 is a PCI bus operated pursuant to the PCI standard which is well known in the art. The computer system shown in FIG. 1a typically also includes a further bus controller 27 which is coupled between the bus 19 and an expansion bus 29. It will be appreciated that typically the processor bus 11 operates at a very high frequency (e.g. 50 MHz) while the bus 19 operates at a slower frequency, and the bus 29 operates at an even slower frequency. Thus, slower operating peripherals are typically coupled to the bus 29, such a floppy disk drive or serial and parallel ports 33 and the BIOS ROM 31.
In the computer system shown in FIG. 1a, the cache 12 is a group of separate integrated circuits (ICs) which are coupled to the processor bus and which are controlled by the system control and cache/DRAM control unit 15. As indicated above, this control unit 15 is typically one or a plurality of so called core logic chips or a chipset which is provided by many different semiconductor companies, including for example Intel Corporation of Santa Clara, Calif., and Cypress Semiconductor Corporation of San Jose.
FIG. 1b shows a simplified version of a portion of FIG. 1a. In particular, FIG. 1b shows a Pentium microprocessor 10a which is coupled via a processor bus having an address portion 11a and a data portion 11b to a plurality of SRAM ICs. A core logic chipset 15a is coupled to the address bus and provides control signals to the SRAM ICs. It will be appreciated that the DRAM and the buses 19 and 29 and the associated components coupled to buses 19 and 29 are not shown in FIG. 1b. In a typical embodiment represented by FIG. 1b, the Pentium microprocessor will be coupled to a 256 kilobyte (KB) cache which is composed of 8 SRAM chips or ICs . Thus, there will be at least one core logic chip and 8 SRAM chips all of which tend to heavily load the address and control lines due to the number of packages and longer traces between the packages which contain the integrated circuits. The system in FIG. 1b also consumes considerable power and also emits a considerable amount of electromagnetic radiation (which tends to cause electromagnetic interference--EMI) due to the number of packages and longer traces on a printed circuit board which is used to hold the Pentium microprocessor as well as the core logic chip or chipset 15a and the 8 SRAM chips 12a through 12h. Two main factors govern the loading at the address lines and control lines (such as the output enable and chip select lines): the number of packages or chips and the trace length on the printed circuit board used to hold the packages. Eight packages alone often present a minimum load of 40 pF. The trace length is largely determined by the physical space required to accommodate the CPU (e.g. the pentium microprocessor or other processors), the chipset which provides the system control, and the cache SRAMs. With eight SRAM chips the trace length can be 6 inches or longer, contributing another 20 to 30 pF to the signal loading. It will be appreciated that the signal loading slows down the operating speed of the system. It will also be appreciated that the electromagnetic radiation emitted from the various tracings and chips also is undesirable.